Device Utilization Summary | [-] |
Slice Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Registers |
5,484 |
30,064 |
18% |
|
Number used as Flip Flops |
5,476 |
|
|
|
Number used as Latches |
1 |
|
|
|
Number used as Latch-thrus |
0 |
|
|
|
Number used as AND/OR logics |
7 |
|
|
|
Number of Slice LUTs |
8,145 |
15,032 |
54% |
|
Number used as logic |
7,769 |
15,032 |
51% |
|
Number using O6 output only |
5,200 |
|
|
|
Number using O5 output only |
384 |
|
|
|
Number using O5 and O6 |
2,185 |
|
|
|
Number used as ROM |
0 |
|
|
|
Number used as Memory |
279 |
3,664 |
7% |
|
Number used as Dual Port RAM |
160 |
|
|
|
Number using O6 output only |
152 |
|
|
|
Number using O5 output only |
2 |
|
|
|
Number using O5 and O6 |
6 |
|
|
|
Number used as Single Port RAM |
90 |
|
|
|
Number using O6 output only |
90 |
|
|
|
Number using O5 output only |
0 |
|
|
|
Number using O5 and O6 |
0 |
|
|
|
Number used as Shift Register |
29 |
|
|
|
Number using O6 output only |
12 |
|
|
|
Number using O5 output only |
0 |
|
|
|
Number using O5 and O6 |
17 |
|
|
|
Number used exclusively as route-thrus |
97 |
|
|
|
Number with same-slice register load |
53 |
|
|
|
Number with same-slice carry load |
44 |
|
|
|
Number with other load |
0 |
|
|
|
Number of occupied Slices |
2,901 |
3,758 |
77% |
|
Number of MUXCYs used |
1,660 |
7,516 |
22% |
|
Number of LUT Flip Flop pairs used |
9,185 |
|
|
|
Number with an unused Flip Flop |
4,172 |
9,185 |
45% |
|
Number with an unused LUT |
1,040 |
9,185 |
11% |
|
Number of fully used LUT-FF pairs |
3,973 |
9,185 |
43% |
|
Number of unique control sets |
535 |
|
|
|
Number of slice register sites lost to control set restrictions |
1,421 |
30,064 |
4% |
|
Number of bonded IOBs |
97 |
186 |
52% |
|
Number of LOCed IOBs |
97 |
97 |
100% |
|
IOB Flip Flops |
92 |
|
|
|
Number of RAMB16BWERs |
27 |
52 |
51% |
|
Number of RAMB8BWERs |
7 |
104 |
6% |
|
Number of BUFIO2/BUFIO2_2CLKs |
1 |
32 |
3% |
|
Number used as BUFIO2s |
1 |
|
|
|
Number used as BUFIO2_2CLKs |
0 |
|
|
|
Number of BUFIO2FB/BUFIO2FB_2CLKs |
1 |
32 |
3% |
|
Number used as BUFIO2FBs |
1 |
|
|
|
Number used as BUFIO2FB_2CLKs |
0 |
|
|
|
Number of BUFG/BUFGMUXs |
9 |
16 |
56% |
|
Number used as BUFGs |
6 |
|
|
|
Number used as BUFGMUX |
3 |
|
|
|
Number of DCM/DCM_CLKGENs |
0 |
4 |
0% |
|
Number of ILOGIC2/ISERDES2s |
9 |
272 |
3% |
|
Number used as ILOGIC2s |
9 |
|
|
|
Number used as ISERDES2s |
0 |
|
|
|
Number of IODELAY2/IODRP2/IODRP2_MCBs |
0 |
272 |
0% |
|
Number of OLOGIC2/OSERDES2s |
66 |
272 |
24% |
|
Number used as OLOGIC2s |
66 |
|
|
|
Number used as OSERDES2s |
0 |
|
|
|
Number of BSCANs |
0 |
4 |
0% |
|
Number of BUFHs |
0 |
160 |
0% |
|
Number of BUFPLLs |
0 |
8 |
0% |
|
Number of BUFPLL_MCBs |
0 |
4 |
0% |
|
Number of DSP48A1s |
3 |
38 |
7% |
|
Number of ICAPs |
1 |
1 |
100% |
|
Number of MCBs |
0 |
2 |
0% |
|
Number of PCILOGICSEs |
0 |
2 |
0% |
|
Number of PLL_ADVs |
1 |
2 |
50% |
|
Number of PMVs |
0 |
1 |
0% |
|
Number of STARTUPs |
0 |
1 |
0% |
|
Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
Average Fanout of Non-Clock Nets |
3.88 |
|
|
|